Highly conductive composite polysilicon gate for cmos integrated circuits

ABSTRACT

Many integrated circuits include a type of transistor known as a metal-oxide-semiconductor, field-effect transistor, or “mosfet,” which has an insulated gate member that controls its operation. Early mosfets had aluminum gates. But because the aluminum made the mosfets unreliable and difficult to manufacture, aluminum was abandoned in favor of polysilicon. Unfortunately, polysilicon has ten-times more electrical resistance than aluminum, which not only wastes power but also slows operation of the integrated circuits. Several efforts have been made to use materials less-resistive than polysilicon, but these have failed to yield a practical solution, since some of the materials have high electrical resistance and prevent low-voltage operation. Accordingly, one embodiment of the invention provides a gate structure that includes a doped polysilicon layer to facilitate low-voltage operation, a diffusion barrier to improve reliability, and a low-resistance aluminum, gold, or silver member to reduce gate resistance. Moreover, to overcome previous manufacturing difficulties, the inventors employ a metal-substitution fabrication technique, which entails formation of a polysilicon gate, and then substitution of metal for the polysilicon.

BACKGROUND OF THE INVENTION

[0001] The present invention concerns fabrication methods and structuresfor integrated circuits, particularly methods and structures forfield-effect transistors.

[0002] Integrated circuits, the key components in thousands ofelectronic and computer products, are interconnected networks ofelectrical components fabricated on a common foundation, or substrate.Fabricators typically use various techniques, such as layering, doping,masking, and etching, to build thousands and even millions ofmicroscopic resistors, transistors, and other electrical components on asilicon substrate, known as a wafer. The components are then “wired,” orinterconnected, together to define a specific electric circuit, such asa computer memory or microprocessor.

[0003] Many integrated circuits include a common type of transistorknown as a metal-oxide-semiconductor, field-effect transistor, or“mosfet” for short. A mosfet has four electrodes, orcontacts—specifically, a gate, source, drain, and body—which connect toother transistors or components to form a circuit. In digital integratedcircuits, such as logic circuits, memories, and microprocessors whichoperate with electrical signals representing ones and zeroes, eachmosfet behaves primarily as a switch, with its gate serving to open andclose a channel connecting its source and drain. Closing the switchrequires applying a certain threshold voltage to the gate, and openingit requires either decreasing or increasing the gate voltage relativethe threshold voltage, depending on whether the channel is made ofnegatively or positively doped semiconductive material.

[0004] One class of mosfet problems concerns the structure andcomposition of its gate. The gates of early mosfets were formed from atwo-layer structure comprising a top aluminum layer and an underlyinginsulative layer, which separates and thus isolates the aluminum fromits underlying semiconductive channel. This structure was a problem notonly because the aluminum diffused through the underlying insulativelayer and destroyed isolation between the gate and underlying channel,but also because the low-melting temperature of aluminum conflicted withhigh-temperature baking, or annealing, steps necessary to properly forma drain and source in alignment with the gate. Thus, for betterreliability and superior drains and sources, contemporary mosfets havegates made, not from aluminum nor any other metal, but frompolycrystalline silicon, sometimes called “polysilicon” or simply,“poly.”

[0005] Polysilicon, which has a multi-crystalline structure instead ofthe single-crystalline structure of silicon wafers, can be alteredthrough doping, a process of adding impurities, to act as a conductor,similar to aluminum but unfortunately with about ten-times moreelectrical resistance. This higher resistance can be ameliorated some bysilicidation, a process of coating and reacting polysilicon with asalicide-forming refractory metal. But, the higher resistance of eventhe salicided polysilicon gates combines with inherentintegrated-circuit capacitances to cause significant delays inconducting signals from one circuit point to another, ultimatelylimiting how fast integrated circuits operate.

[0006] In response, several efforts have been made to form gates frommaterials less-resistive than polysilicon or polysilicon salicides. Forexample, D. H. Lee and coworkers have proposed making gates fromtungsten (W) and titanium nitride (TiN). (See “Gate Oxide Integrity(GOI) of MOS Transistors with W/TiN Stacked Gate,” Symposium on VLSITechnology, Honolulu, pp. 208-209, 1996.) In addition, a team led by J.M. Hwang has proposed a gate consisting of stacked layers of polysiliconand titanium nitride. (See “Novel Polysilicon/TiN Stacked-Gate Structurefor Fully-Depleted SOI/CMOS,” Digest IEEE International Electron DevicesMeeting, San Francisco, pp. 345-348, 1992.) Similarly, another group,headed by S. L. Wu, has proposed a gate structure consisting ofstacked-amorphous-silicon film. (See “Suppression of the BoronPenetration Induced Si/SiO₂ Interface Degradation by Using aStacked-Amorphous-Silicon Film as the Gate Structure for Pmosfet,” IEEEElectron Device Letters, vol. 15, no. 5, pp 160-162, May 1994.)

[0007] However, each of these efforts has failed to yield a practicalsolution. In particular, the electrical properties of the materials inthese proposed gate structures, namely tungsten and titanium nitride,limit how low mosfet threshold voltages can be set, and thus pose abarrier to low-voltage operation, a necessity for increasingbattery-life in portable computers, telephones, etc. Moreover, theelectrical resistance of tungsten and titanium nitride is at least twicethat of metals such as aluminum, gold, or silver.

[0008] Therefore, there remains a need not only for mosfets withlower-resistance gate structures, but also for suitable methods ofmaking them.

SUMMARY OF THE INVENTION

[0009] To address these and other needs, the inventors developedlow-resistance metal gate structures for field-effect transistors, andmethods for making these structures. Specifically, one embodiment of thegate structure includes an aluminum, gold, or silver top layer to reducegate resistance, a middle diffusion barrier layer to improvereliability, and a doped polysilicon bottom layer to facilitatelow-voltage operation. Thus, the gate structure overcomes severaldrawbacks of both early metal gates and conventional polysilicon gates.

[0010] One method for making the low-resistance gate structure entailsforming a gate insulation layer on a semiconductive channel region,forming a polysilicon structure on the gate insulation layer, and thensubstituting metal, preferably aluminum, gold, or silver, for at least aportion of the polysilicon structure to form the gate. In the preferredembodiment, the metal substitution involves depositing a metal layer onthe polysilicon structure and then heating it and the polysiliconstructure to urge cross-diffusion of the metal and polysilicon. In stillother embodiments, the method includes implanting source and drainregions before depositing the metal layer, and thereby eliminates thetemperature conflicts that prevented the use of metals, such asaluminum, with conventional source and drain self-alignment techniques.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011]FIG. 1 is a cross-sectional view of an integrated-circuit assemblyduring one stage of a fabrication process;

[0012]FIG. 2 is a cross-sectional view of the FIG. 1 integrated-circuitassembly after formation of four layers 18 a-18 d;

[0013]FIG. 3 is a cross-sectional view of the FIG. 2 assembly afterforming a gate stack 20, sidewall spacers 22 a and 22 b, and drain,source, and channel regions 24 d, 24 c, and 24 s;

[0014]FIG. 4 is a cross-sectional view of the FIG. 3 assembly afterremoval of layer 18 d and formation of two layers 28 and 30; and

[0015]FIG. 5 is a cross-sectional view of the FIG. 4 assembly after ametal substitution reaction and planarization procedures form metal gatecontact 28′;

[0016]FIG. 6 is a block diagram of a genericdynamic-random-access-memory circuit that incorporates field-effecttransistors having low-resistance gate structures according to thepresent invention;

[0017]FIGS. 7A is a cross-sectional view of an integrated-circuitassembly illustrating an RF application of the low-resistance gatestructure of the present invention; and

[0018]FIG. 7B is a top view of the FIG. 7A assembly, illustrating itscontact layout.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] The following detailed description, which references andincorporates FIGS. 1-7B, describes and illustrates specific embodimentsof the invention. These embodiments, offered not to limit but only toexemplify and teach the invention, are shown and described in sufficientdetail to enable those skilled in the art to implement or practice theinvention. Thus, where appropriate to avoid obscuring the invention, thedescription may omit certain information known to those of skill in theart.

[0020] FIGS. 1-5 show a number of preferred integrated-circuitassemblies, which taken collectively and sequentially, illustrate thepreferred method of fabricating a field-effect transistor according tothe present invention. FIG. 6 shows a preferred embodiment of adynamic-random-access-memory circuit incorporating the field-effecttransistor of the present invention. And, FIGS. 7A and 7B illustrate anRF (high-frequency) application of the invention, specifically anassembly of interdigitated field-effect transistors.

Preferred Method and Structure for Field-Effect Transistor

[0021] The method, as shown in FIG. 1, begins with a knownintegrated-circuit assembly or structure 10, which includes a substrate12. The term “substrate,” as used herein, encompasses a semiconductorwafer as well as structures having one or more insulative,semi-insulative, conductive, or semiconductive layers and materials.Thus, for example, the term embraces silicon-on-insulator,silicon-on-sapphire, and other advanced structures.

[0022] In addition to substrate 12, assembly 10 includes a gateinsulation layer 14 and shallow-trench-isolation (STI) regions 16 a and16 b. Gate insulation layer 14 and isolation regions 16 a and 16 bpreferably consist of a silicon oxide, such as silicon dioxide. Thesestructures are preferably formed through conventional CMOS processing.

[0023] As shown in FIG. 2, the preferred method next forms a gatesubassembly 18 comprising four layers 18 a, 18 b, 18 c, and 18 d. Thisformation first entails growing or depositing a 50-nanometer-thick layer18 a of doped polysilicon. For dual-work-function NMOS or PMOS devices,the polysilicon should be respectively doped with an n-type or p-typedopant to set a desired threshold voltage of the transistor underconstruction. The second layer is a 50-nanometer-thick, diffusionbarrier layer 18 b, which consists of polycrystalline ormicrocrystalline silicon carbide, polycrystalline silicon oxycarbide,titanium nitride, amorphous silicon or other suitablemetal-diffuision-barring material. The third layer 18 c, formed on layer18 b, is a 500-nanometer-thick layer of polysilicon. The method thenforms the fourth layer, a 100-200 nanometer-thick silicon nitride(Si₃N₄) gate cap layer 18 d, atop layer 18 c.

[0024] Preferably, the formation of layers 18 a, 18 b, and 18 c entailsa “continuous” deposition process with temporary compositional changesto form the respective layers. In addition, layer 18 c is planarizedconventionally using chemical-mechanical polishing, before formation ofgate cap layer 18 d using chemical-vapor deposition.

[0025]FIG. 3 shows the results of forming gate subassembly 18 into agate stack 20, adding sidewalls 22 a and 22 b to gate stack 20, anddefining respective drain, channel, and source regions 24 d, 24 c, and24 s. Forming subassembly 18 into gate stack 20 involves conventionallypatterning the gate and then etching through all four layers of gatesubassembly 18 down to gate insulation layer 14. This process entailsfirst etching gate cap layer 18 d to form an etch mask which defines theshape and size of the gate and then etching layers 18 a, 18 b, and 18 cto conform to the etch mask. The resulting gate stack 20 includes layers20 a-20 d, which correspond in composition and thickness to respectivelayers 18 a-18 d.

[0026] Subsequent to the etching, the method forms respectiveself-aligned drain and source regions 24 d and 24 s in substrate 12,using conventional ion-implantation techniques. Although a lightly dopeddrain (LDD) profile is presently preferred, any desirable profile may bechosen. Other embodiments use, for example, an abrupt junction or a“fully overlapped, lightly doped drain” (FOLD) profile. To achieve thepreferred profile, the method forms insulative sidewall spacers 22 a and22 b on opposing sidewalls of gate stack 20, before executing theion-implantation procedure which forms drain and source regions 24 d and24 s.

[0027] Drain and source regions are formed using conventional ionimplantation and subsequent high-temperature (900-1000° C.) annealing.In conventional processing, these annealing temperatures preclude theuse of aluminum and other metals having melting temperatures less thanthe anneal temperature. The preferred implantation doses are 10¹⁵ persquare centimeter. Formation of drain and source regions 24 d and 24 salso defines the length of semiconductive channel region 24 c.Optionally, one may salicide the junctions according to conventionalmethods.

[0028]FIG. 4 shows the results of the next series of operations. First,the method passivates the assembly by forming an insulative fill layer26 matching the thickness of gate stack 20. The preferred technique isthermal oxidation, oxide deposition, or a combination of the two. Aplanarization procedure, preferably chemical-mechanical polishing,follows to remove any passivation matter overlying gate cap 20 d. Themethod then uses phosphoric acid to remove gate cap 20 d, therebyexposing polysilicon layer 20 c. At this point in the process, theintegrated-circuit assembly in FIG. 4 constitutes a conventionalfield-effect transistor with polysilicon gate contact and self-alignedsource and drain regions.

[0029] After removing gate cap 20 d, the method uses evaporation,sputtering, or chemical vapor deposition to form a 1.5-micron-thick,metal layer 28 on the now-exposed polysilicon layer 18 c and surroundingportions of passivation layer 26. Although the preferred embodimentforms metal layer 28 from an aluminum alloy, which includesapproximately 0.3 to 4.0 percent copper and 0.3 to 1.6 percent siliconto reduce electromigration of the aluminum at high current levels, otherembodiments (described below) use gold or silver. Indeed, the inventorsbelieve that virtually any metal that will substitutionally dissolve inpolysilicon or a polysilicon germanium alloy could be used successfully.

[0030] Next as FIG. 4 shows, the method forms a 200-nanometer-thick,titanium layer 30 on metal layer 28 by evaporation, sputtering, orchemical vapor deposition. In other embodiments, layer 30 is between 20and 250 nanometers thick and comprises zirconium or hafnium, instead oftitanium. Layer 30, which is optional, reduces the temperature and timenecessary to complete the next step.

[0031] The next step forces a metal-substitution reaction between metallayer 28 and polysilicon layer 20 c. To force this reaction betweenaluminum and polysilicon, the preferred method heats, or anneals, theintegrated-circuit assembly to approximately 450° C. in a nitrogen,forming gas, or other non-oxidizing atmosphere for approximately 60minutes. Heating urges diffusion or dissolution of metal layer 26 intopolysilicon layer 20 c and polysilicon layer 20 c into the metal layer,ultimately substituting metal for most, if not all, of the polysiliconlayer 20 c. The substitution process is bounded by diffusion barrierlayer 20 b and spacers 22 a and 22 b.

[0032] Although here the substitution has been presented in theparticularly desirable context of forming a metal gate member for afield-effect transistor, the method may be readily adapted, preferablywith the provision of substitution boundary structures, to form anycontact or electrode of a transistor or of another integrated-circuitcomponent. Moreover, the substitution technique can also be applied toform a low-resistance wiring level on, for example, STI region 16 a or16 b or any area of substrate 12. It may also be used to form aluminumplugs. See Hiroshi Horie et. al, “Novel High Aspect Ratio Aluminum Plugfor Logic/DRAM LSIs Using Polysilicon-Aluminum Substitute (PAS),”(Technical Digest IEEE International Electron Devices Meeting, SanFrancisco, pp. 946-948, 1996) which is incorporated herein by reference.

[0033] At the conclusion of the substitution reaction, the methodremoves superficial polysilicon and remaining portions of layers 28 and30 through conventional planarization. FIG. 5 shows the resultinglow-resistance composite gate structure comprising a low-resistancemetal gate contact 28′ atop polysilicon diffusion barrier 20 b, whichitself lies atop doped polysilicon layer 20 a. In contrast toconventional gates which have a relatively high-resistance polysilicongate contact, this preferred gate structure provides a conductive metallayer, which has a much lower electrical resistance. Estimates are thatthe electrical resistance of the preferred gate structure is less thanhalf that of conventional polysilicon gates.

[0034] With completion of the composite gate structure, conventionaltechniques may be used to form drain and source contacts (not shown).Additionally, conventional interconnection techniques may be used toconnect metal gate contact 28′ and the drain and source contacts to eachother, to one or more contacts of other similar or differenttransistors, or to other components to make a complete integratedcircuit. The preferred method ultimately concludes by heat-treating theintegrated circuit for one to six hours at a temperature between 100 and200° C. This heat treatment, which preferably occurs after packaging theintegrated circuit in a protective housing, ensures that the metal gatecontacts as well as other metal interconnections have minimumresistivity.

[0035] Other embodiments of the field-effect transistor and fabricationmethod form metal gate contact 28′ from metals other than the preferredaluminum alloy. For example, other embodiments form the gate contactfrom more conductive, but costlier metals, such as gold and silver. Inthese embodiments, layers 18 c and 20 c comprises a polycrystallinesilicon-germanium alloy with 10 to 60 percent germanium. Theseembodiments require different annealing temperatures to effect the metalsubstitution reaction. In general, the annealing, or substitution,temperature should not exceed the eutectic temperature of the metallicsystem comprising metal layer 28 and layer 18 c. In particular, to forma gold gate contact one would form layer 28 from gold and anneal atapproximately 300° C., and to form a silver gate contact one would formlayer 28 from silver and anneal at approximately 500-600° C. In theseembodiments, it is also preferable to use zirconium, which has a lowersolubility than titanium and hafnium in silver and gold, to formoptional layer 30. In the aluminum embodiment, layer 18 c may alsocomprise polysilicon and germanium, in which case the anneal temperatureis reduced to approximately 400° C., instead of 450° C.

[0036] In addition, other embodiments omit barrier layer 20 b. Incontrast to the preferred embodiment where this layer not only preventsdiffusion of gate metal into gate insulation 14, but also facilitatescontrol of the metal-substitution process, embodiments lacking barrierlayer 20 b are somewhat less reliable and more difficult to make.

Preferred Embodiment of an Integrated Memory Circuit Incorporating theField-Effect Transistor

[0037]FIG. 6 shows one example of the unlimited number of applicationsfor transistors having the low-resistance gate structure of the presentinvention: a generic dynamic-random-access-memory (DRAM) circuit 40.DRAM circuit 40 includes a number of subcircuits, which typicallycomprise one or more field-effect transistors. More precisely, DRAMcircuit 40 includes a memory array 42 which comprises a number of memorycells 43, a column address decoder 44, and a row address decoder 45, bitlines 46, word lines 47, and voltage-sense-amplifier circuit 48 coupledin conventional fashion to bit lines 46.

[0038] In the preferred embodiment, each of the memory cells, theaddress decoders, and the amplifier circuit includes one or morefield-effect transistors that has the low-resistance gate structure ofthe present invention. However, in other embodiments, only one of thecomponents, for example, memory array 42 or voltage-sense-amplifiercircuit 48, includes field-effect transistors with the low-resistancegate structure. Circuit 40 operates according to well-known andunderstood principles.

Preferred Embodiment of High-Frequency Integrated-Circuit AssemblyIncorporating the Field-Effect Transistor

[0039] The invention also has application to RF circuits, where it iscritical to provide low gate resistance. For this reason, conventionalRF applications use gallium-arsenide (GaAs) field-effect transistors.However, the low-resistance gate structure of the present inventionmakes it possible to use silicon CMOS field-effect transistors (fets),instead of GaAs fets, in RF applications, such as low-noise amplifiers,mixers, oscillators, and power amplifiers. In such applications, fetshaving the low-resistance gate structure of the present inventionprovide performance comparable to GaAs fets with the advantage ofhigher-density integration.

[0040]FIG. 7A and 7B show respective cross-sectional and top views of anovel portion of an integrated-circuit assembly 50 for a conventionalhigh-frequency amplifier, mixer, oscillator, or power amplifier.(Complete circuits for these devices are well-known and thus need not bereproduced here.) Assembly 50 features substantially identical,n-channel CMOS fets 60, 70, and 80 which have interdigitated drain andsource regions. More particularly, fet 60 has respective drain, channel,and source regions 61, 62, and 63 in substrate 51. Fet 60 shares source63 with fet 70, which similarly shares drain 71 with fet 80. Insuccessive layers atop channel region 62 lie gate insulation layer 64,doped polysilicon layer 65 a, diffusion barrier layer 65 b, and metalgate contact 66. The gate structures of fets 70 and 80 follow similarlywith respective metal gate contacts 76 and 86, diffusion barrier layers75 b and 85 b, doped polysilicon layers 75 a and 85 a, and gateinsulation layers 74 and 84. The metal gate contacts are preferablyformed and composed as detailed above. (Note that for clarity,structures analogous to sidewall spacers 22 a and 22 b and passivationlayer 26 have been omitted from the figure.)

[0041]FIG. 7A also shows the cross-section of contacts 67, 68, 77, and88. Drain contact 67 contacts drain region 61 of fet 60; source contact67 contacts source region 63 of fet 60 and source region 73 of fet 70;drain contact 77 contacts drain region 71 of fet 70 and drain region 81of fet 80; and source contact 88 contacts source region 83.

[0042]FIG. 7B presents a top view of the assembly, which details theinterconnections of the metal gate contacts, the drain contacts, and thesource contacts. Specifically, FIG. 7B shows that metal gate contacts66, 76, and 86 are electrically connected to gate metal interconnect 56,to form a comb-like interconnect structure with the metal gate contactsas teeth. In addition, FIG. 7B shows that drain contacts 67 and 77 areelectrically connected to each other by a metal interconnect 57, andsource contacts 68 and 88 are electrically connected via a metalinterconnect 58. Interconnect 57 includes a cross-over 59, preferably anair bridge, to isolate interconnect 57 from interconnect 58.Interconnects 56 and 57 and cross-over 59 are formed using conventionalinterconnection processes.

Conclusion

[0043] Embodiments of the present invention provide practical structuresand fabrication methods for field-effect transistors with metal gates.One specific gate structure includes an aluminum, gold, or silver toplayer to reduce gate resistance, a middle diffusion barrier layer toimprove reliability, and a doped polysilicon bottom layer to facilitatelow-voltage operation. One method embodiment forms source and drainregions prior to formation of the metal gate via a metal substitutiontechnique, thereby precluding exposure to the metal-melting temperaturesoccurring during source and drain formation. Thus, the present inventionovercomes drawbacks of early metal-gated transistors which wereunreliable and difficult to manufacture, contemporary transistors whichhave more-resistive polysilicon gates, and recently proposed gatestructures that prevent low-voltage operation.

[0044] The embodiments described above are intended only to illustrateand teach one or more ways of practicing or implementing the presentinvention, not to restrict its breadth or scope. The actual scope of theinvention, which embraces all ways of practicing or implementing theinvention, is defined only by the following claims and theirequivalents.

1. A method of making an insulated metal gate for a transistor, themethod comprising: forming a gate insulation layer; forming apolysilicon structure on the gate insulation layer; and substitutingmetal for at least a portion of the polysilicon structure.
 2. The methodof claim 1, wherein forming the polysilicon structure comprises: forminga first polysilicon layer on the gate insulation layer; forming adiffusion barrier layer on the first polysilicon layer; and forming asecond polysilicon layer on the diffusion barrier layer.
 3. The methodof claim 2, wherein the first polysilicon layer includes a dopant todefine a threshold voltage for the transistor.
 4. The method of claim 2,wherein the diffusion barrier layer comprises at least one of thefollowing: a silicon carbide, a silicon oxycarbide, a titanium nitride,and an amorphous silicon.
 5. The method of claim 2, wherein the secondpolysilicon layer includes polysilicon and germanium.
 6. The method ofclaim 1 wherein substituting metal for the polysilicon layer comprisessubstituting metal for substantially all of the polysilicon layer. 7.The method of claim 1 wherein substituting metal for at least a portionof the polysilicon structure, comprises: depositing metal on thepolysilicon structure; and urging diffusion of the deposited metal intothe polysilicon layer.
 8. The method of claim 7, wherein urgingdiffusion of the deposited metal and the polysilicon structurecomprises: heating the deposited metal and the polysilicon structure toa predetermined temperature.
 9. The method of claim 1 whereinsubstituting metal for at least a portion of the polysilicon structurecomprises: forming a metal layer on the polysilicon structure; andheating the metal layer and the polysilicon structure to a predeterminedtemperature.
 10. The method of claim 1 wherein the metal comprises atleast one of aluminum, gold, and silver.
 11. The method of claim 1wherein the polysilicon structure includes one or more layers.
 12. Amethod of making an insulated metal gate for a transistor, the methodcomprising: forming a gate insulation layer; forming a polysiliconstructure on the gate insulation layer, the polysilicon structureincluding: a first polysilicon layer on the gate insulation layer; adiffusion barrier layer on the first polysilicon layer; and a secondpolysilicon layer on the diffusion barrier layer; and substituting metalfor at least a portion of the second polysilicon layer.
 13. The methodof claim 12, wherein the first polysilicon layer includes a dopant todefine a threshold voltage for the transistor.
 14. The method of claim12, wherein the diffusion barrier layer comprises at least one of thefollowing: a silicon carbide, a silicon oxycarbide, a titanium nitride,and an amorphous silicon.
 15. The method of claim 12, wherein the secondpolysilicon layer includes polysilicon and germanium.
 16. The method ofclaim 12 wherein substituting metal for the polysilicon layer comprisessubstituting metal for substantially all of the polysilicon layer. 17.The method of claim 12 wherein substituting metal for at least a portionof the second polysilicon layer, comprises: depositing metal on thesecond polysilicon layer; and heating the deposited metal and thepolysilicon structure to a predetermined temperature.
 18. The method ofclaim 12 wherein the metal comprises at least one of aluminum, gold, andsilver.
 19. A method of making an insulated metal gate for a transistor,the method comprising: forming a gate insulation layer; forming apolysilicon structure on the gate insulation layer, the polysiliconstructure including: a doped polysilicon layer on the gate insulationlayer to define a threshold voltage for the transistor; a diffusionbarrier layer on the first polysilicon layer; and a second polysiliconlayer on the diffusion barrier layer, the second polysilicon layerincluding polysilicon and germanium; and depositing metal including atleast one of aluminum, gold, and silver on the second polysilicon layer;and heating at least the deposited metal and the second polysiliconstructure to urge diffusion of the deposited metal into the secondpolysilicon layer.
 20. The method of claim 19, wherein the diffusionbarrier layer comprises at least one of the following: a siliconcarbide, a silicon oxycarbide, a titanium nitride, and an amorphoussilicon.
 21. A method of making a field-effect transistor having aself-aligned metal gate, the method comprising: depositing or growing agate insulation structure on a semiconductive layer; depositing orgrowing a polysilicon structure on the gate insulation structure;forming self-aligned source and drain regions in the semiconductivelayer after depositing or growing the polysilicon structure, the sourceand drain regions aligned with the polysilicon structure; andsubstituting metal for at least a portion of the polysilicon structureafter forming the self-aligned source and drain regions to form a metalgate aligned with the source and drain regions.
 22. The method of claim21 wherein forming the source and drain regions comprises ionimplantation and annealing.
 23. The method of claim 21: wherein thepolysilicon structure includes: a first polysilicon layer on the gateinsulation layer; a diffusion barrier layer on the first polysiliconlayer; and a second polysilicon layer on the diffusion barrier layer;and wherein substituting metal for at least a portion of the polysiliconstructure includes substituting metal for substantially all of thesecond polysilicon layer.
 24. The method of claim 23, wherein the firstpolysilicon layer includes a dopant to define a threshold voltage forthe transistor.
 25. The method of claim 23, wherein the diffusionbarrier layer comprises at least one of the following: a siliconcarbide, a silicon oxycarbide, a titanium nitride, and an amorphoussilicon.
 26. The method of claim 23, wherein the second polysiliconlayer includes polysilicon and germanium.
 27. The method of claim 23wherein substituting metal for substantially all of the secondpolysilicon layer, comprises: depositing metal on the second polysiliconlayer; and heating at least the deposited metal and the polysiliconstructure to a predetermined temperature.
 28. The method of claim 21wherein the metal comprises at least one of aluminum, gold, and silver.29. A method of making a metal gate for a field effect transistor, whichcomprises depositing or growing a gate insulation structure on asemiconductive layer; depositing or growing a polysilicon-based gate onthe gate insulation structure; and substituting metal for at least aportion of the polysilicon-based gate.
 30. The method of claim 29further comprising forming source and drain regions in thesemiconductive layer in alignment with the polysilicon-based gate beforesubstituting metal for at least a portion of the polysilicon-based gate.31. A method of making a metal electrode for a transistor, the methodcomprising: forming a semiconductive region of the transistor; forming apolysilicon structure on the semiconductive region; and substitutingmetal for at least a portion of the polysilicon structure.
 32. Anintegrated-circuit assembly for making an electrode for a transistor,the assembly comprising: a semiconductive layer; a metal-substitutablelayer adjacent the semiconductive layer; and a first metal layercontacting the metal-substitutable layer.
 33. The assembly of claim 32wherein the metal-substitutable layer comprises at least one ofpolysilicon and germanium, and the first metal layer comprises at leastone of aluminum, gold, and silver.
 34. The assembly of claim 32 furthercomprising: a doped polysilicon layer contacting the semiconductivelayer; a diffusion barrier layer between the doped polysilicon layer andthe metal-substitutable layer; and a second metal layer contacting thefirst metal layer, the second metal layer including at least one ofhafnium, zirconium, and titanium.
 35. A gate structure for afield-effect transistor, comprising: a gate insulation structurecontacting a channel region of the transistor; a doped polysilicon layercontacting the gate insulation structure, the polysilicon layer doped todefine a threshold voltage for the transistor; a diffusion barrier layeradjacent the doped polysilicon layer; and a metal layer contacting thediffusion barrier layer.
 36. The assembly of claim 35 wherein the metallayer comprises at least one of aluminum, gold, and silver, and thediffusion barrier layer comprises at least one of the following: asilicon carbide, a silicon oxycarbide, a titanium nitride, and anamorphous silicon.
 37. An integrated memory circuit comprising: a memoryarray having a plurality of memory cells; an address decoder coupled tothe memory cells; a plurality of bit lines coupled to the memory cells;a voltage-sense-amplifier circuit coupled to the bit lines; and whereinat least one of the memory cells and the voltage-sense amplifier circuitincludes a field-effect transistor comprising: a gate insulationstructure contacting a channel region of the transistor; a dopedpolysilicon layer contacting the gate insulation structure, thepolysilicon layer doped to define a threshold voltage for thetransistor; a diffusion barrier layer adjacent the doped polysiliconlayer; and a metal layer contacting the diffusion barrier layer andcomprising at least one of aluminum, gold, and silver.
 38. Anintegrated-circuit assembly, comprising: a plurality of field-effecttransistors formed on a silicon substrate, with at least two transistorssharing a common source or drain region; and wherein at least onetransistor includes: a gate insulation structure contacting a channelregion of the one transistor; a doped polysilicon layer contacting thegate insulation structure, the polysilicon layer doped to define athreshold voltage for the one transistor; and a diffusion barrier layeradjacent the doped polysilicon layer; and a metal layer contacting thediffusion barrier layer.